The present invention relates generally to integrated circuits and testing integrated circuits and, more particularly, to a method and system for testing an integrated circuit using Logic Built-in Self-test (LBIST).
Integrated circuits, such as microprocessors or system-on-chip (SOC) devices typically include a complex matrix of logic gates arranged to perform particular functions. These logic gates are often interconnected in two parallel arrangements, one for operation, and another for testing circuit functionality. Linking a plurality of latches together into a “scan chain” is one known method of arranging logic gates for testing. Such scan chains may be used to gain access to internal nodes of the integrated circuit. Test patterns are shifted in by the scan chains and functional clock signals are pulsed to test the circuit during a capture cycle. The results are then shifted to output pins and compared against expected results. This test cycle is typically repeated many times, which, given the size of integrated circuits today, makes scan test time consuming.
One known method for generating test data for application to the scan chains is LBIST (Logic Built-In Self-Test), which is widely used to detect certain manufacturing defects. LBIST is also a useful tool for studying hardware power and frequency characteristics. However, the electrical power generated during a full-chip LBIST scan can become unreasonably high, sometimes exceeding tolerable levels. Shift speeds and therefore LBIST run time are limited by the current consumption of the device under test. Another problem associated with LBIST testing, particularly at start-up, is the creation of a large voltage drop, which can lead to failures.
Thus it would be advantageous to provide a built-in self-testing system that mitigates these disadvantageous effects.